The present invention relates to an intermediate voltage generating circuit for supplying voltage having various levels to the gate and drain of a memory cell.
Hitherto, a nonvolatile semiconductor memory, such as an EPROM or EEPROM, requires voltage having various levels when it performs read, program, erase and verify operations, as shown in
TABLE 1 ______________________________________ GATE DRAIN SOURCE MODE VOLTAGE Vg VOLTAGE Vd VOLTAGE Vs ______________________________________ READ 5 V 0.8 V 0 V PROGRAM 10 V 5 V 0 V ERASE -10 V 0 V 5 V VERIFY 3.5 V, 5 V, 7.5 V 0.8 V 0 V ______________________________________
For example, voltage Vg of a control gate of a memory cell is set to be 10 V when a program operation is performed, the same is set to be -10 V when an erase operation is performed, and the same is set to be 3.5 V, 5 V or 7.5 V when a verify operation is performed.
On the other hand, a nonvolatile semiconductor memory, such as a NOR flush memory developed recently, has been enabled to be operated with a single power source set to be 3.3 V in place of the conventional method using two power sources consisting of 5 V and 12 V power sources. If the single power source set to be 3.3 V is used, the various voltage levels shown in Table 1 are generated in a charge pump circuit in the LSI.
That is, the nonvolatile semiconductor memory using the single power source set to be 3.3 V is required to perform the program operation, the verify operation and so forth by quickly and accurately generating voltage having a predetermined level with respect to 3.3 V.
An automatic program mode will now be discussed as an example of a mode which must quickly switch the voltage.
FIGS. 1A and 1B are flow charts of the automatic program mode.
In the automatic program mode, the address is set initially, and then the program and verify operations are performed. If the verify operation has been performed successfully, the program operation is again performed. If the verify operation has been performed unsuccessfully, a recovery operation is performed to restore the original state.
At this time, for example, the voltage Vg of the word line is continuously changed as 5 V (when the address is set).fwdarw.{10 V (when the program operation is performed).rarw..fwdarw.7.5 V (when the verify operation is performed): a predetermined number of times is repeated}.fwdarw.5 V (when the recovery operation is performed).
To perform the automatic program mode in a short time, the foregoing transition of the voltage levels must quickly be completed.
FIG. 2 shows a voltage generating system for generating voltage of various levels.
A charge pump circuit 11 generates boosted voltage VPP. A reference voltage generating circuit 12 generates reference voltage VREF. An intermediate voltage generating circuit 13 generates output voltage VOUT having various levels from the boosted voltage VPP with respect to the reference voltage VREF.
Hitherto, the reference voltage generating circuit 12 is classified into a zener diode type reference circuit, a widlar type BGR (Band Gap Reference Circuit), and the like.
FIG. 3 shows the zener diode type reference voltage generating circuit. The foregoing reference voltage generating circuit comprises a current source 14 and a zener diode 15. However, the reference voltage generating circuit required high voltage has a problem in that the voltage level required for the LSI cannot be lowered.
FIG. 4 shows the widlar BGR. The reference voltage generating circuit comprises bipolar transistors 16 to 19, resistors 20 to 22 and a current source 23. However, the foregoing reference voltage generating circuit having the bipolar transistors 16 to 19 encounters a difficulty in including a process for manufacturing the bipolar transistors in a process for manufacturing a MOS transistor. Thus, the foregoing reference voltage generating circuit has a problem in that it cannot widely be used. Although a parasitic bipolar transistor, which can be manufactured by the CMOS manufacturing process, may be employed, the characteristics of the parasitic bipolar transistor are changed excessively attributable to the density of the well to be employed practically.
FIG. 5 shows an example of the structure of the conventional intermediate voltage generating circuit.
Reference voltage VREF is supplied to a negative input terminal of a current mirror differential amplifying circuit 31. The gate of a pull-up P-channel MOS transistor TP1 is connected to an output terminal of the current mirror differential amplifying circuit 31. An N-channel MOS transistor TN1 is connected between the gate of the MOS transistor TP1 and the grounded point.
Boosted voltage VPP of the charge pump circuit is applied to the source of the MOS transistor TP1, while output voltage VOUT is output from the drain of the same. Resistors R1 and R2 and MOS transistors TP2 and TN2 connected in parallel to each other are, in series, connected between the drain of the MOS transistor TP1 and the grounded point.
Junction B between the resistors R1 and R2 is connected to the positive input terminal of the differential amplifying circuit 31.
An N-channel MOS transistor TN3 and a depression type N-channel MOS transistor DN1 are, in series, connected between the drain of the MOS transistor TP1 and the grounded point. The gate and source of the MOS transistor DN1 are connected to each other.
Control signal SEAN is supplied to the gate of each of the MOS transistors TN1 and TP2, while control signal SEAN is supplied to the gate of each of the MOS transistors TN2 and TN3.
In the intermediate voltage generating circuit having the above-mentioned structure, the current mirror differential amplifying circuit 31 detects and amplifies the difference between the reference voltage VREF and the voltage VB at the junction B. In accordance with the output from the differential amplifying circuit 31, the pull-up P-channel MOS transistor TP1 is driven so as to maintain the output voltage VOUT at a constant level.
The output voltage VOUT of the intermediate voltage generating circuit and the voltage VB at the junction B have the relationship expressed by the following Equation (1): EQU (R2.times.VOUT)/(R1+R2)=B (1)
where R1 and R2 are resistance levels of the resistors R1 and R2.
That is, when VB=VREF, the output voltage VOUT has a constant value. Even if the level of the boosted voltage VPP is deflected and thus the output voltage VOUT is somewhat varied, the amount of variation is fed back to the differential amplifying circuit 31. As a result, the output voltage VOUT can immediately be stabilized.
Rise of the output voltage VOUT occurring when a sub-threshold leak current in the pull-up P-channel MOS transistor TP1 is allowed to flow is prevented by the depression type N-channel MOS transistor DN1. The reason for this is that the depression type MOS transistor DN1 serves as a constant current source for allowing a constant current to flow such that it does not depend upon the boosted voltage VPP.
When the intermediate voltage generating circuit is not operated, the control signal SAEN is set to be the "H" level.
When the control signal SAEN is at the "H" level, the MOS transistor TN1 is turned on. On the other hand, the MOS transistors (the transfer gates) TP2 and TN2 and the MOS transistor TN3 are turned off. That is, output node A of the current mirror differential amplifying circuit 31 is made to be ground voltage VSS so that the MOS transistor TP1 is brought to a state where it is always operated. Since the MOS transistors TP2, TN2 and TN3 have been turned off, the output voltage VOUT is made to be the boosted voltage VPP.
When the intermediate voltage generating circuit is operated to obtain the predetermined output voltage VOUT, the control signal SAEN is required to be set to the "L" level.
When the control signal SAEN is made to be the "L" level, the MOS transistor TN1 is turned off and the MOS transistors (the transfer gates) TP2 and TN2 and the MOS transistor TN3 are turned on.
Since output node C has been electrically charged to the boosted voltage VPP at this time, an electric current flows from the output node C to the grounded point through the MOS transistors TP2 and TN2 and the resistors R1 and R2.
Since the voltage VB at the junction B is higher than the reference voltage VREF immediately after the control signal SAEN has been made to be the "L" level, the current mirror differential amplifying circuit 31 outputs voltage having the "H" level to retain the pull-up MOS transistor TP1 to be turned off.
Therefore, the charge in the output node C is gradually discharged. When the voltage VB at the junction B has been made to be the same as the reference voltage VREF, the intermediate voltage generating circuit outputs the constant output voltage VOUT.
However, the conventional intermediate voltage generating circuit mainly uses the passage which is allowed to pass through the resistors R1 and R2 to discharge the charge in the output node C.
That is, if the levels of the resistors R1 and R2 are raised to reduce electric power consumption, there arises a problem in that an excessively long time is required to realize the predetermined output voltage VOUT after the output node C has been electrically charged to the boosted voltage VPP.
If the levels of the resistors R1 and R2 are lowered to quickly obtain the predetermined output voltage VOUT, there arises a problem in that the electric current consumption is enlarged.
As described above, the conventional intermediate voltage generating circuit involves that the requirement for the reduction of the power consumption and the requirement for raise the operation speed have the trade-off relationship. Therefore, the two requirements cannot simultaneously be satisfied.
FIG. 6 shows another example of the structure of the conventional intermediate voltage generating circuit.
Reference voltage VREF is supplied to the negative input terminal of the current mirror differential amplifying circuit 31. The gate of a pull-up P-channel MOS transistor TP1 is connected to an output terminal of the current mirror differential amplifying circuit 31. The differential amplifying circuit 31 is controlled in response to enable signal ENA such that the differential amplifying circuit 31 is made to be operable when the enable signal ENA is "H" level.
Boosted voltage VPP of the charge pump circuit is applied to the source of the MOS transistor TP1, while output voltage VOUT is output from the drain of the same. Resistors R1 and R2 are, in series, connected between the drain of the MOS transistor TP1 and the grounded point. Junction B of the resistors R1 and R2 is connected to the positive input terminal of the differential amplifying circuit 31.
An N-channel MOS transistor TN4 is connected between the drain of the MOS transistor TP1 and the grounded point. The gate of the MOS transistor TN4 is supplied with inverted signal ENA of the enable signal.
An N-channel MOS transistor TN5 is connected between the drain of the MOS transistor TP1 and the grounded point. The MOS transistor TN5 has relatively small size to prevent rise of the output voltage VOUT occurring due to overshoot, sub-threshold leak current, charge coupling or the like.
A capacitor C1 is connected between the drain of the MOS transistor TP1 and the grounded point. The capacitor C1 is provided for the purpose of compensating phase delay for the feedback loop of the differential amplifying circuit 31 so as to stabilize the output voltage VOUT.
In the intermediate voltage generating circuit having the above-mentioned structure, the current mirror differential amplifying circuit 31 detects and amplifies the difference between the reference voltage VREF and the voltage VB at the junction B. In accordance with the output from the differential amplifying circuit 31, the pull-up P-channel MOS transistor TP1 is driven so that the output voltage VOUT is retained at a constant level.
The output voltage VOUT from the intermediate voltage generating circuit and the voltage VB at the junction B have the relationship expressed by the above-mentioned Equation (1).
That is, when VB=VREF, the output voltage VOUT has a constant value. Even if the level of the boosted voltage VPP is deflected and thus the output voltage VOUT is somewhat varied, the amount of variation is fed back to the current mirror differential amplifying circuit 31. Thus, the output voltage VOUT can immediately be stabilized.
Rise of the output voltage VOUT occurring due to overshoot, capacity coupling with the power source, the sub-threshold leak current of the pull-up P-channel MOS transistor TP1 or the like is prevented by the N-channel MOS transistor TN5 having the relatively small size. That is, the MOS transistor TN5 always lowers the level of the output voltage VOUT.
The differential amplifying circuit 31 has a current mirror circuit composed of a P-channel MOS transistor which has excellent consistency with the MOS transistor TP1 in order to drive the P-channel MOS transistor TP1. That is, the current mirror circuit of the differential amplifying circuit 31 is composed of a MOS transistor having the same conduction type as that of the MOS transistor which is driven by the differential amplifying circuit 31.
As a result, the cut off characteristics of the intermediate voltage generating circuit can be improved and an error occurring when the stable state has been realized can be prevented.
The capacitor C1 compensates phase delay for the feedback loop of the differential amplifying circuit 31 so as to stabilize the output voltage VOUT.
When the intermediate voltage generating circuit is not operated, the enable signal ENA must be set to be "L" level.
When the enable signal ENA is "L" level, the voltage level of the output node A of the differential amplifying circuit 31 is made to be the same as the power supply voltage VDD. Thus, the P-channel MOS transistor TP1 is turned off. Moreover, the N-channel MOS transistor TN4 having the gate to which the inverted signal ENA of the enable signal is supplied is turned on. Therefore, the output voltage VOUT is made to be the level of the ground voltage VSS.
When the intermediate voltage generating circuit is operated to obtain the predetermined output voltage VOUT, the enable signal ENA must be set to be "H" level.
When the enable signal ENA is made to be "H" level, the P-channel MOS transistor TP1 is turned on and the N-channel MOS transistor TN4 is turned off.
At this time, an electric current is supplied from the charge pump circuit to the output node C so that the voltage level of the output node C is made to be the constant output voltage VOUT.
However, the conventional intermediate voltage generating circuit having the above-mentioned structure, as shown in FIG. 7, has a problem in that the output voltage VOUT is oscillated and an excessively long time is required for the output voltage VOUT to be stabilized to a constant level.
As described above, the requirement for reducing the power consumption and that for raising the operation speed of the intermediate voltage generating circuit have not simultaneously been satisfied. Moreover, the output voltage cannot quickly be stabilized to a constant voltage level because of the oscillation of the output voltage.